I am asking this because I am trying to implement interrupts in my toy kernel. So, I know that when an interrupt occurs, the CPU pushes various bits of information onto the stack. However, everywhere I search online shows different information in different order being pushed. I also know that if the interrupt occurred in user mode (Ring 3), the CPU must switch to kernel mode (Ring 0) before it can execute the ISR. I think it has something to do with the TSS and ss and esp, however I am not sure. I have read various different explanations all over the internet and have not found any uniformity in any of them yet.
So my question is, in what exact order does the (x86) CPU push data onto the stack during an interrupt and when does it do it, and at what point in time does it make a context switch via the TSS and how does this affect the data that is pushed onto the stack, if at all?
What I have learned from research so far (correct me if wrong): I am pretty sure the processor pushes eflags, cs and eip onto the stack as well as an error code if necessary during an interrupt. However, is this all that is pushed? I have read elsewhere that ss and esp are pushed but I don't know if this happens all the time, or why it is pushed.
Furthermore, I believe that the CPU will look in the TSS for the Ring0 ss and esp and at some point load them, but I am not sure when. Perhaps it does this right after the interrupt occurs? Also, how is cs and ds handled during all of this? Is cs loaded by the CPU from the entry in the IDT? What about ds? Must I load that manually?
Sorry if this is the wrong place to ask, I am not sure where else I should.
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