if-statement - 操纵时钟信号以获得10个脉冲(Manipulate a clocked signal in order to get 10 pulses)

Question

I am attempting to create a very specific signal in my code.

(我试图在代码中创建一个非常具体的信号。)

Basically I need a signal to be generated after load_0 ends, in the falling edge, where such signal would be 10 pulses of the 1KHz signal and the rest 0. Which is just preserving 10 pulses that are aligned with the variable Serial_out.

(基本上，我需要在load_0结束后的下降沿生成一个信号，该信号将是1KHz信号的10个脉冲，其余0个。仅保留与变量Serial_out对齐的10个脉冲。)

Thus far I have tried an if to attempt this, with a counter to attempt to count to 10 for the 10 pulses i want and discarding the rest.

(到目前为止，我已经尝试过是否尝试这种操作，并使用计数器尝试对我想要的10个脉冲计数到10，然后丢弃其余的脉冲。)

This always ends either not being able to be synthesized due to error or the test bench clk_trig never being initialized.

(这总是由于错误而无法合成或永远不会初始化测试平台clk_trig。)

My coding is quite crude due to the fact that I have not been using xilinx for long.

(由于我没有使用xilinx很久了，所以我的编码非常粗糙。)

Main section of the code

(代码的主要部分)

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY HAMMING IS
    PORT ( CLK_50MHz_M : IN  STD_LOGIC;
             RST  : IN STD_LOGIC;
             LOAD_O : IN STD_LOGIC;
             input1 : IN STD_LOGIC;
             input2 : IN STD_LOGIC;
             input3 : IN STD_LOGIC;
             input4 : IN STD_LOGIC;
             input5 : IN STD_LOGIC;
             input6 : IN STD_LOGIC;
             CLK_DIV_O : OUT STD_LOGIC;
             CLK_TRIG : OUT STD_LOGIC;
             Serial_out : OUT STD_LOGIC);
END HAMMING;

ARCHITECTURE ARCH OF HAMMING IS
SIGNAL input_vec : STD_LOGIC_VECTOR(6 DOWNTO 1);
SIGNAL output : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL CLK_100Hz, CLK_50KHz : STD_LOGIC;


COMPONENT P2S
     port(
         clk : in STD_LOGIC;
         reset : in STD_LOGIC;
         load : in STD_LOGIC;
         din : in STD_LOGIC_VECTOR(9 downto 0);
         dout : out STD_LOGIC);
END COMPONENT;

COMPONENT SCALE_CLOCK
        PORT (CLK_50MHz_S : IN  STD_LOGIC;
                RST       : IN  STD_LOGIC;
                CLK_100Hz   : OUT STD_LOGIC);
END COMPONENT;

begin
----------------------------------------------
process (LOAD_O, CLK_100Hz)
begin
    if (LOAD_O = '1') then CLK_TRIG <= '0';    -crude attempt at the desired signal
    ELSE
    CLK_TRIG <= CLK_100Hz;
    end if;
end process;
---------------------------------------------

-- BITS DE PALABRA
output(2) <= input_vec(1);
output(4) <= input_vec(2);
output(5) <= input_vec(3);
output(6) <= input_vec(4);
output(8) <= input_vec(5);
output(9) <= input_vec(6);

-- BIT PARIEDAD
output(0) <= input_vec(1) XOR input_vec(2) XOR input_vec(4) XOR input_vec(5);
output(1) <= input_vec(1) XOR input_vec(3) XOR input_vec(4) XOR input_vec(6);
output(3) <= input_vec(2) XOR input_vec(3) XOR input_vec(4);
output(7) <= input_vec(5) XOR input_vec(6);

ClockDiv: SCALE_CLOCK PORT MAP(CLK_50MHz_S => CLK_50MHz_M, RST => RST, CLK_100Hz => CLK_100Hz);
SeriesOut: P2S PORT MAP(clk => CLK_100Hz, din => output, dout =>  Serial_out, reset => RST, load => LOAD_O);

CLK_DIV_O <= CLK_100Hz;
input_vec <= input1 & input2 & input3 & input4 & input5 & input6;
END ARCH;

FPGA2 code running

(FPGA2代码正在运行)

  ask by Mak Buck translate from so

Answer 1

You have a 50MHz clock.

(您有一个50MHz的时钟。)
from that you probably decided to make a nice 50/50 100Hz clock and then use that.

(因此，您可能决定制作一个不错的50/50 100Hz时钟，然后使用它。)
That is the wrong strategy!

(那是错误的策略！)

You always want as much as possible a synchronous design.

(您总是希望尽可能多地进行同步设计。)

If you want signals to change at 100Hz the right (synchronous) method is as follows:

(如果您希望信号以100Hz的频率变化，则正确的（同步）方法如下：)

• Make 100Hz pulses which are high for one 50MHz clock only.

  (产生仅对一个 50MHz时钟为高的100Hz脉冲。)

  (eg P100Hz)

  (（例如P100Hz）)

• Everywhere you use a 100Hz clock go back to using the 50 MHz clock then in the 50MHz clock section use an additional if P100Hz then

  (在使用100Hz时钟的任何地方，请回到使用50MHz时钟的位置，然后在“ 50MHz时钟”部分中， if P100Hz then)

You now have a synchronous design running at effectively 100Hz.

(您现在有了一个同步设计，其有效运行频率为100Hz。)