ascii - 如何将ASCII码转换为Verilog语言中的字符(How can I convert ASCII code to characters in Verilog language)

Question

I've been looking into this but searching seems to lead to nothing.

(我一直在研究，但搜索似乎无济于事。)

It might be too simple to be described, but here I am, scratching my head... Any help would be appreciated.

(描述起来可能太简单了，但是在这里，我挠头...任何帮助将不胜感激。)

  ask by ParSa translate from so

Answer 1

Verilog knows about "strings".

(Verilog知道“字符串”。)

A single ASCII character requires 8 bits.

(一个ASCII字符需要8位。)

Thus to store 8 characters you need 64 bits:

(因此，要存储8个字符，您需要64位：)

wire [63:0] string8;

assign string8 = "12345678";

There are some gotchas:

(有一些陷阱：)

• There is no End-Of-String character (like the C null-character)

  (没有字符串结尾字符（如C空字符）)

• The most RHS character is in bits 7:0.

  (最多的RHS字符在7：0位中。)
  Thus string8[7:0] will hold 8h'38.

  (因此string8 [7：0]将保持8h'38。)

  ("8").

  (（“ 8”）。)

• To walk through a string you have to use eg: string[ index +: 8];

  (要遍历字符串，您必须使用例如： string[ index +: 8];)

• As with all Verilog vector assignments: unused bits are set to zero thus

  (与所有Verilog向量分配一样：未使用的位设置为零，因此)
  assign string8 = "ABCD"; // MS bit63:32 are zero

• You can not use two dimensional arrays:

  (您不能使用二维数组：)
  wire [7:0] string5 [0:4]; assign string5 = "Wrong";