makefile - Do Not interpret as Make variable in Make command

Question

I have this code in a Makefile:

$(TCLNAME).batch.tcl: $(TCLNAME).tcl
      echo source $::env(TOOLS_DIR)/my.tcl > $@

What I want to be printed in $(TCLNAME) is: source $::env(TOOLS_DIR)/my.tcl

But I get an error because $::env(TOOLS_DIR) is being interpreted as a Make variable and it is expecting ( after the $.

How do I make it to print that line as is and not interpret it as Make variable ? I tried to use escape character such as $::env(TOOLS_DIR) but that also did not work.

question from:https://stackoverflow.com/questions/65622909/do-not-interpret-as-make-variable-in-make-command

Answer 1

Escape the $ with another $, and the parentheses with backslashes:

$(TCLNAME).batch.tcl: $(TCLNAME).tcl
    echo source $$::env(TOOLS_DIR)/my.tcl > $@