Desinging a content addressable memory (cam) in verilog

Question

currently learning verilog and what I'm trying to do is designing a content addressable memory (cam) in the following ways:

1. Fully parallel
2. Bit serial - Word parallel
3. Bit parallel - Word serial

So far I've managed to implement the first one, but having a hard time to implement the other two since I'm pretty new to this. Here is what I've done so far for the first type:

module pp_cam(
    ck,   // clock
    en,   // enable
    din,  // content value
    dout  // content location
);

parameter ADDR_WIDTH  = 2;
parameter DEPTH       = 1 << ADDR_WIDTH;

input ck, en;
input [3:0] din;
output reg [ADDR_WIDTH-1:0] dout;

reg [3:0] mem [DEPTH-1:0];
reg [ADDR_WIDTH-1:0] loc;
integer i;

initial begin
    mem[0] = 4'b1101; // 13
    mem[1] = 4'b1100; // 12
    mem[2] = 4'b0101; // 5
    mem[3] = 4'b0001; // 1
end

always @(din) begin
    loc = {ADDR_WIDTH{1'bx}};
    for (i = 0; i < DEPTH; i = i+1) begin
        if (mem[i] == din)
          loc = i;
    end
end
    
always @(posedge ck) begin
    if (en)
        dout <= loc;
        $display("%b", loc);
    else
        dout <= {ADDR_WIDTH{1'bx}};
end

endmodule

Looking forward to implement the other two types based on the first implementation, but got stuck. Any help or tips that could help me would be much appreciated.

question from:https://stackoverflow.com/questions/65944662/desinging-a-content-addressable-memory-cam-in-verilog

Answer 1

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