assembly - 65(C)02 Will indexed zero page addressing cross page boundary?

Question

I'm building an emulator for the 6502 and 65C02 and I don't have the actual chip (yet).
I tried looking this up in the datasheet but it doesn't say what will happen when this occurs:

LDA #$FF    ; 0xFF -> A
LDX #$20    ; 0x20 -> X

STA #$F4, X
; A -> M[0x00F4 + X]
; A -> M[0x00F4 + 0x20]
; A -> M[0x0114] ?
; OR
; A -> M[(0x00F4 + X) & 0x00FF]
; A -> M[(0x00F4 + 0x20) & 0x00FF]
; A -> M[0x0114 & 0x00FF]
; A -> M[0x0014] ?

STA with a single byte address will store the result in the zero page. But if the offset crosses the page boundary, will it be written to the next page over (stack) or will it stay on the zero page and wrap around?

Is it the same behavior for the 6502 NMOS and 65C02 CMOS?

Will the page boundary cross for the zero page add an additional clock cycle as it does for absolute addressing modes with indexing?

question from:https://stackoverflow.com/questions/65940159/65c02-will-indexed-zero-page-addressing-cross-page-boundary

Answer 1

No. The carry during the addition of the index will not be used.