In AVR architecture the registers are located at the first 32 address in data memory space as appears in the following picture.
the address of the register could be representable in 5 bits in the instruction opcode to know exactly where is the 5 bit in the opcode, you have to look at AVR instruction set Manual and see every instruction binary
for example if you look at the page 115 in the manual you will see the translation in binary for LDi instruction which is limit you to only access the upper 16 register (from r16 to r31) the 16 is represented only in the 4 bit, so it appears in the third Nibble as litter d (d abbreviation for "destination register") Note: if dddd bits take one value from 0000 to 1111 this will map from r16 to r31
I cannot figure out which registers are supposed to be r10 and r20
let us manually translation this code ClR R10 to opcode to figure out the answer
in the manual (page 71) you will find that the ClR is Just EOR (Exclusive OR) which mean
clr R10
; is same opcode as
EOR R10,R10
now try to found EOR translation instead of ClR, in manual (Page 91) you will found the following
EOR Rd,Rr
;will translat to
;0010 01rd dddd rrrr
now replace RdandRr with r10 (r10 in binary will be 01010)
so the output will be
;be carful in bits location
;the bits are mixed
0010 01rd dddd rrrr
0010 0100 1010 1010
this is the translate of CLR R10
now try to translate ROR r20 by yourself (hint : ROR in page 145)
What I can figure out is, at least I believe, that registers X and Y are $004A and $004B respectively
this is not correct, X Y and Z registers are actually pairs of r27:r26, r29:r28 and r31:r30 registers
indirect store instruction ST will be translated for different opcode depend on which pairs are selected (x, y, z work as alias for these pairs) and you could see them in pages 173-177 in the manual
