simulation - I cannot see some signals within a bus during simultaion - verilog

Question

I designed a module named wishbone, responsible for some actions (it is a top module which is supposed to interconnect other modules to accomplish a certain function). Also, within the wishbone module, one can notice that only "a batch" of signals provide useful data at a time, thus, for instance, when wr_data_instructions signal from wishbone module is active, there will be involved only wr_data_instructions and rd_data_instructions signals. Consequently, I decided to use a single bus in order to be shared by all those signals. Nevertheless, I come across some issues, because the simulation doesn't seem to work, as long as I cannot see the "in" (now I commented the "in" signal within the module instantiation because it caused a warning) signal or "o" signal etc. Here is the code for the wishbone module:

//wishbone module
module wishbone(
    input clk,rst,
    output reg [2:0]in,
    output reg wr_en_instructions,wr_en_display,
    input [2:0] wr_data_instructions,//created for usr, in order to make possible to write data
    output reg [3:0] wr_data_display,
    output [2:0] rd_data_instructions,
    output [3:0] rd_data_display,//created for user, in order to make possible the display
    output [12:0]o
);

reg [15:0] pointer_instructions,pointer_display;

initial wr_en_instructions = 1'b1;//not necessary
/*
by element X it is ment sizeof(X), i.e. number of lines within the bus
pointer_instructions + wr_data_instructions + rd_data_instructions
pointer_display + wr_dara_display + rd_data_display
3 + 3 = 6 => requires 6 lines
4 + 4 = 8 => requires 8 lines
=> requires 8 (max(6,8))
encoding:
case 1 (wr_en_instructions):
wr_data_instrucitons: [2:0]
rd_data_instructions: [5:3]
case 2 (~wr_en_instructions):
wr_data_display: [3:0]
rd_data_display: [7:4]
*/
control_unit i0(.clk(clk),.rst(rst),.in(in),.o(o));
user i1(.clk(clk),.wr_en(wr_en_instructions),.address_in(pointer_instructions),.wr_data(wr_data_instructions),.rd_data(rd_data_instructions));
display i2(.clk(clk),.wr_en(wr_en_display),.address_in(pointer_display),.wr_data(wr_data_display),.rd_data(rd_data_display));
integer i = 0;
always @ * begin
    wr_en_display = ~wr_en_instructions;
end
always @(posedge clk) begin
    if(rst) begin
        wr_en_instructions <= 1'b1;
        pointer_instructions <= 16'd0;
        pointer_display <= 16'd0;
    end
    else begin
        if(wr_en_instructions) begin
            if(wr_data_instructions[2] == 1'b1) begin
                pointer_instructions <= 16'd0;
                pointer_display <= 16'd0;
                wr_en_instructions <= 1'b0;
            end
        end
        else begin
            in <= rd_data_instructions;
            pointer_instructions <= pointer_instructions + 1;
            if(rd_data_instructions == 3'b010) begin
                wr_data_display <= o;
                pointer_display <= pointer_display + 1;
            end
            else if(rd_data_instructions == 3'b100) begin
               wr_en_instructions <= 1'b1;
            end
        end
    end
end

endmodule

and here is the code for my top module that uses the wishbone module:

    `include "wishbone.v"
/*
by element X it is ment sizeof(X), i.e. number of lines within the bus
pointer_instructions + wr_data_instructions + rd_data_instructions
pointer_display + wr_dara_display + rd_data_display
3 + 3 = 6 => requires 6 lines
4 + 4 = 8 => requires 8 lines
=> requires 8 (max(6,8))
encoding:
case 1 (wr_en_instructions):
wr_data_instrucitons: [2:0]
rd_data_instructions: [5:3]
case 2 (~wr_en_instructions):
wr_data_display: [3:0]
rd_data_display: [7:4]
*/
module bus(
  input clk,rst,//clock and reset signals for wishbone
  output [2:0] in,//input
  output chip_select,//wr_en_instructions or ~wr_en_display
  output chip_select_b,//~wr_en_instructions or wr_en_display
  inout [7:0] wishbone_bus,//wishbone bus
  output [12:0] o//output
);

reg [2:0] wr_data_instrucitons;
wire [2:0] rd_data_instructions;
wire [3:0] wr_data_display,rd_data_display;

wishbone i0(
    .clk(clk),.rst(rst),
    .in(in),
    .wr_en_instructions(chip_select),//2:1 multiplexer
    .wr_en_display(chip_select_b),//2:1 multiplexer
    .wr_data_instructions(wr_data_instrucitons),
    .wr_data_display(wr_data_display),
    .rd_data_instructions(rd_data_instructions),
    .rd_data_display(rd_data_display),
    .o(o)
);

always @ * begin
    if(chip_select) begin
        wishbone_bus[2:0] = wr_data_instrucitons;
        wishbone_bus[5:3] = rd_data_display;
    end
    else begin
        wr_data_display = wishbone_bus[3:0];//how to solve?
        wishbone_bus[7:4] = rd_data_display;
    end
end

endmodule

and finally here is my testbench:

//bus testbench
module bus_tb(
    output reg clk,rst,
    output [2:0]in,
    output wr_en_instructions,wr_en_display,
    output reg [2:0] wr_data_instructions,//created for usr, in order to make possible to write data
    output [3:0] wr_data_display,
    output [2:0] rd_data_instructions,
    output [3:0] rd_data_display,//created for user, in order to make possible the display
    output [12:0]o
);

wire [7:0] wb;

assign wb = wr_en_instruction ?
            {1'b0,1'b0,rd_data_instructions,wr_data_instructions} :
            {rd_data_display,wr_data_display};

bus cut(
    .clk(clk),.rst(rst),
    .chip_select(wr_en_instruction),
    .chip_select_b(wr_en_display),
    //.in(in),
    .wishbone_bus(wb),
    .o(o)
);

initial $dumpvars(0,bus_tb);

initial begin
    clk = 1'b1;
    repeat (600000)
    #100 clk = ~clk;
end

initial begin
    rst = 1'b1;
    #400 rst = 1'b0;
end

initial begin
    wr_data_instructions = 3'd1;
    #3000400 wr_data_instructions = 3'd2;
    #1000000 wr_data_instructions = 3'd1;
    #3000000 wr_data_instructions = 3'd0;
    #2000000 wr_data_instructions = 3'd3;
    #1000000 wr_data_instructions = 3'd1;
    #3000000 wr_data_instructions = 3'd4;//halt
end

endmodule

.

question from:https://stackoverflow.com/questions/65898839/i-cannot-see-some-signals-within-a-bus-during-simultaion-verilog

Answer 1

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