verilog - Frequency of Montgomery Multiplier

Question

I have designed a 16*16 Montgomery multiplier. The code uses a 16*16 multiplier to perform three multiplications. The multiplications are performed one after the other using the same multiplier and the result of each multiplication is stored in the registers. The single 16*16 multiplier performs at a frequency of about 1550 MHz, but the frequency of the Montgomery multiplier (which uses a single 16*16 multiplier three times) is reduced to almost 500 MHz when the three multiplications are carried out in series. I want to avoid the decrease in frequency and want to operate it at the frequency of single multiplier. Need help in this.

The code is provided along with.(only multiplications are provided in this case. Additions, shifting has been excluded for simplicity)

`define m 11
`define mbar 245
module test_mul(a,b,clk,reg2,reset);

input [15:0] a,b;
input clk,reset;
output reg [31:0] reg2;


reg [15:0] x,y;

reg [31:0] reg0,reg1;
reg [5:0] count;

wire [31:0]p;


test_mul16 a1 (x,y,clk, p);


always @ (posedge clk)
begin
if (reset)
begin  x <= a; y <= b; count= 6'd0 end

else begin

if (count == 11)
reg2 <= p;
if (count == 12)
begin x <= reg0[15:0]; y <=`mbar; end
if (count == 27)
reg1 <= p;
else if (count == 28)
begin
x <= reg1[15:0];
y <= `m;
end
else if (count == 39)
begin
reg2 <= p;
end

count = count+1;

end
end

endmodule

module test_mul16(a,b,clk,reg2);

input [15:0] a,b;
input clk;
output reg [31:0] reg2;

reg [31:0] reg0, reg1;
always @ (posedge clk)
begin
reg0<= a*b;
reg1<=reg0;
reg2<=reg1;
end
endmodule

Answer 1

Ok, so based on the comment where Hida says that this is a timing issue, I think there could be a couple things going on here. I can help you improve timing, but I am not certain that we can get to 1.5Ghz. You should let us know which vendor you are using too.

You have a if with a reset, but you do not reset all variables. That is okay as long as you know that you don't have anything uninitialized. But the real thing here is that many new FPGA technologies, don't want you to use reset if you don't have to. I notice that you are reseting, x and y with inputs a and b. Do you have to do this? If you do not have to reset, x and y to a and b respectively, you can remove them from the reset and this will help timing improve.

Your state machine, (using the variable state) is not one hot. You may look at coding that to use one hot and that will give you a little boost.

To do this, make count a 40 bit registers, reset it to 40'h00001, and then on clock assign it as such count <= {count[38:0],count[39]}; then use the individual bit to trigger your logic.

Next, take a look at your if's You have a bunch of one-off if's. In some cases, you have multiple if's assigning the same variable. This probably okay, but the synthesizer is probably having to work some things out, and it might not be as efficient as it could be if you coded it differently. Try using a case statement. If you follow the one-hot suggestion above your case statements will be like this case(count) 40'd11 : begin do some stuff end 40'd12 : begin do some other stuff end etc... endcase

Finally, also in your IF's, you have some if and if else going on. Get those massaged into this case statement above, because you are basically assignably priority to counts 27, 28 and 39. For one variable, there can and should be no priority between the values. The value is either 27, 28 or 39, or something else, and the logic will never have a case to choose one state over another.

If you make some of those changes, your speed should go up. Would really like to know which vendor is saying you hit 1.5Ghz though.