vhdl - HDMI Pass Through with RGB Switch Filter

Question

I'm very new to VHDL and FPGAs, and have hit a rock. Im currently working on video filters on the zybo z7-10, and started off using this guide to create a HDMI passthrough on the board: https://github.com/dpaul24/hdmi_pass_through_ZyboZ7-10?_ga=2.34188391.796043983.1579510279-2100398226.1578999679

So after getting that working all i want to do is be able to effect the video output. To do this, I tried to set the rgb 24 bit vectors last 8 bits to 0, removing all blue from the output. If i try the following code (with or without the process block) i get a syntax error on the "if" statement line

process is 
begin
    if sw ='0' then
        vid_pData(7 downto 0) <= sw
    end if;
end process;

The issue is I don't seem to be able to put this anywhere in the code without causing an error. Can someone explain what's happening here?

Full code below:

---

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity hdmi_pass_top is
    Port ( 
        sysclk_i         : in  std_logic; -- 125MH System Clock Input
        async_reset_i    : in  std_logic; -- Reset switch on board

        -- HDMI In/Rx
        tmds_rx_clk_p_i  : in  std_logic;
        tmds_rx_clk_n_i  : in  std_logic;
        tmds_rx_data_p_i : in  std_logic_vector(2 downto 0);
        tmds_rx_data_n_i : in  std_logic_vector(2 downto 0);
        hdmi_rx_hpd_o    : out std_logic := '1'; -- HPD must be driven
        -- I2C
        sda_io           : inout std_logic;
        scl_io           : inout std_logic;

        -- HDMI Out/Tx
        tmds_tx_clk_p_o  : out std_logic;
        tmds_tx_clk_n_o  : out std_logic;
        tmds_tx_data_p_o : out std_logic_vector(2 downto 0);
        tmds_tx_data_n_o : out std_logic_vector(2 downto 0);    

        sw               : in std_logic
         );
end hdmi_pass_top;


architecture hdmi_pass_top_arc of hdmi_pass_top is

component dvi2rgb_0
  port (
    TMDS_Clk_p    : in std_logic;
    TMDS_Clk_n    : in std_logic;
    TMDS_Data_p   : in std_logic_vector(2 downto 0);
    TMDS_Data_n   : in std_logic_vector(2 downto 0);
    RefClk        : in std_logic;
    aRst          : in std_logic;
    vid_pData     : out std_logic_vector(23 downto 0);
    vid_pVDE      : out std_logic;   
    vid_pHSync    : out std_logic;
    vid_pVSync    : out std_logic;
    PixelClk      : out std_logic;
    aPixelClkLckd : out std_logic;
    SDA_I         : in std_logic;
    SDA_O         : out std_logic;
    SDA_T         : out std_logic;
    SCL_I         : in std_logic;
    SCL_O         : out std_logic;
    SCL_T         : out std_logic;
    pRst          : in std_logic
  );
end component;

component rgb2dvi_0
  PORT (
    TMDS_Clk_p  : out std_logic;
    TMDS_Clk_n  : out std_logic;
    TMDS_Data_p : out std_logic_vector(2 downto 0);
    TMDS_Data_n : out std_logic_vector(2 downto 0);
    aRst        : in std_logic;
    vid_pData   : in std_logic_vector(23 downto 0);
    vid_pVDE    : in std_logic;
    vid_pHSync  : in std_logic;
    vid_pVSync  : in std_logic;
    PixelClk    : in std_logic
  );
end component;


component clk_wiz_0
port
 (-- Clock in ports
  -- Clock out ports
  clk_out1          : out    std_logic;
  -- Status and control signals
  reset             : in     std_logic;
  locked            : out    std_logic;
  clk_in1           : in     std_logic
 );
end component;

signal vid_pData          : std_logic_vector(23 downto 0);
signal vid_pVDE           : std_logic;
signal vid_pHSync         : std_logic;
signal vid_pVSync         : std_logic;
signal pixelclk           : std_logic;
signal locked             : std_logic;
signal clk_200M           : std_logic;
signal pixel_clk_sync_rst : std_logic;

signal sda_i              : std_logic;
signal sda_o              : std_logic;
signal sda_t              : std_logic;
signal scl_i              : std_logic;
signal scl_o              : std_logic;
signal scl_t              : std_logic;

begin

clkwiz_inst : clk_wiz_0
   port map ( 
  -- Clock out ports  
   clk_out1 => clk_200M,
  -- Status and control signals                
   reset   => async_reset_i,
   locked  => locked,
   -- Clock in ports
   clk_in1 => sysclk_i
 );

dvi2rgb_inst : dvi2rgb_0
  port map (
    TMDS_Clk_p    => tmds_rx_clk_p_i,
    TMDS_Clk_n    => tmds_rx_clk_n_i,
    TMDS_Data_p   => tmds_rx_data_p_i,
    TMDS_Data_n   => tmds_rx_data_n_i,
    RefClk        => clk_200M,
    aRst          => async_reset_i, --Active high asynchronous RefClk reset
    vid_pData     => vid_pData,
    vid_pVDE      => vid_pVDE,
    vid_pHSync    => vid_pHSync,
    vid_pVSync    => vid_pVSync,
    PixelClk      => pixelclk,
    aPixelClkLckd => open, -- 
    SDA_I         => sda_i,
    SDA_O         => sda_o,
    SDA_T         => sda_t,
    SCL_I         => scl_i,
    SCL_O         => scl_o,
    SCL_T         => scl_t,
    pRst          => '0'   -- Active high PixelClk synchronous reset
  );


SDA_IOBUF_inst: IOBUF
    generic map(
    DRIVE      => 12,
    IOSTANDARD => "DEFAULT",
    SLEW       => "SLOW"
    )
    port map(
    O  => sda_i,  -- Buffer output
    IO => sda_io, -- Buffer inout port(connect directly to top-level port)
    I  => sda_o,  -- Bufferinput
    T  => sda_t   -- 3-state enable input,high=input,low=output
    ); 



SCL_IOBUF_inst: IOBUF
    generic map(
    DRIVE      => 12,
    IOSTANDARD => "DEFAULT",
    SLEW       => "SLOW"
    )
    port map(
    O  => scl_i,  -- Buffer output
    IO => scl_io, -- Buffer inout port(connect directly to top-level port)
    I  => scl_o,  -- Buffer input
    T  => scl_t   -- 3-state enable input,high=input,low=output
    ); 

rgb2dvi_inst : rgb2dvi_0
  port map (
    TMDS_Clk_p  => tmds_tx_clk_p_o,
    TMDS_Clk_n  => tmds_tx_clk_n_o,
    TMDS_Data_p => tmds_tx_data_p_o,
    TMDS_Data_n => tmds_tx_data_n_o,
    aRst        => async_reset_i,
    vid_pData   => vid_pData,
    vid_pVDE    => vid_pVDE,
    vid_pHSync  => vid_pHSync,
    vid_pVSync  => vid_pVSync,
    PixelClk    => pixelclk
  );

end hdmi_pass_top_arc;

---

EDIT: changed my if statement to

vid_pData(7 downto 0) <= "00000000" when sw = '0';

and it got rid of the error but the implementation failed. The failure is:

[DRC MDRV-1] Multiple Driver Nets: Net dvi2rgb_inst/U0/GenerateBUFG.ResyncToBUFG_X/vid_pData[0] has multiple drivers: vid_pData_reg[0]/Q, and dvi2rgb_inst/U0/GenerateBUFG.ResyncToBUFG_X/poData_reg[0]/Q.

Answer 1

You're not writing software, you're designing hardware. Your extra code drives signal vid_pData. So, does component dvi2rgb_0. So you have two drivers on that signal. A short circuit in other words.

Also, you do not say what value vid_pData should take if sw is not equal to '0'. Therefore, you will get latches in your hardware. (Google "inferring a latch".)

You need a new signal, eg:

signal vid_pData_new      : std_logic_vector(23 downto 0);

then you need to assign a value for both sw equals '0' and '1', otherwise you will get a latch:

vid_pData_new(7 downto 0) <= vid_pData(23 downto 8) & "00000000" when sw = '0' else vid_pData;

The & operator is the concatenation operator. Finally, you need to drive component rgb2dvi_0 with your new signal:

rgb2dvi_inst : rgb2dvi_0
  port map (
    TMDS_Clk_p  => tmds_tx_clk_p_o,
    TMDS_Clk_n  => tmds_tx_clk_n_o,
    TMDS_Data_p => tmds_tx_data_p_o,
    TMDS_Data_n => tmds_tx_data_n_o,
    aRst        => async_reset_i,
    vid_pData   => vid_pData_new,   --  <-----------------
    vid_pVDE    => vid_pVDE,
    vid_pHSync  => vid_pHSync,
    vid_pVSync  => vid_pVSync,
    PixelClk    => pixelclk
  );

---

Can you see what has been done here? We have inserted a new piece of hardware that drives the new signal vid_pData_new and have specified its value for both possible values of sw. We must do this, otherwise we will get latches. We are designing hardware, not writing software.