caching - Line size of L1 and L2 caches

Question

From a previous question on this forum, I learned that in most of the memory systems, L1 cache is a subset of the L2 cache means any entry removed from L2 is also removed from L1.

So now my question is how do I determine a corresponding entry in L1 cache for an entry in the L2 cache. The only information stored in the L2 entry is the tag information. Based on this tag information, if I re-create the addr it may span multiple lines in the L1 cache if the line-sizes of L1 and L2 cache are not same.

Does the architecture really bother about flushing both the lines or it just maintains L1 and L2 cache with the same line-size.

I understand that this is a policy decision but I want to know the commonly used technique.

Answer 1

In core i7 the line sizes in L1 , L2 and L3 are the same: that is 64 Bytes. I guess this simplifies maintaining the inclusive property, and coherence.

See page 10 of: https://www.aristeia.com/TalkNotes/ACCU2011_CPUCaches.pdf