makefile - Define compilation variables based on target for

Question

my c++ source file look for a specific variable passed from the makefile. when making a different target, this variable definition is different.

How can I define a variable in Makefile based on target.

Thanks

Answer 1

You can use target-specific variable values, they propagate to target's prerequisites:

all : foo bar
foo : CXXFLAGS += -DFOO
bar : CXXFLAGS += -DBAR

foo bar :
    @echo target=$@ CXXFLAGS=${CXXFLAGS}

.PHONY : all