assembly - Are ARM instructuons SWI and SVC exactly same thing?

Question

ARM assembly has SWI and SVC instructions for entering into 'supervisor mode'.

What confuses me is, why there are two of them? Here it is said that SVC was formerly SWI. Does it mean that basically they changed the mnemonic? Are they the same thing? Can I use them interchangeably? Does one of them exist before an architecture, and other after?

Answer 1

Yes, SWI and SVC are same thing, it is just a name change. Previously, the SVC instruction was called SWI, Software Interrupt.

The opcode for SVC (and SWI) is partially user defined (bit 0-23 is user defined and is like a parameter to SVC handler). Bits 24-27 are b1111 and these 4 bits makes CPU to realize that the opcode is SVC (or SWI). see ARM Information Center for more details.