APB design and testbench port declaration issue using verilog and xilinx vivado

Question

I am trying to design a APB write cycle using Verilog and Xilinx vivado. I am new to verilog, so there are 100 percent possibility that my logic must be wrong. i am getting an error in testbench file where DUT has been declared. Sometimes get this error in 'paddr' sometimes in 'prdata' now getting it for 'pwdata'. i am just trying to implement the write and read cycle simultaneously. I don't know if this is possible or not, but still i could not understand the error.

Design file:

enter code here
module apb_master (pclk,prst,paddr,pwdata,prdata,pwrite,pread,psel,penable,pready);

parameter S_IDLE = 3'b000;
parameter S_SETUP = 3'b001;
parameter S_ACCESS = 3'b010;
input pclk;
input prst;
output reg [3:0] paddr;
output reg [7:0] pwdata;
output reg [7:0] prdata;
output reg pwrite;
output reg psel;
output reg penable;
output reg pread;
input  pready;
//input  wire pslverr;
reg [2:0] state, next_state;
reg Tr;
reg [7:0] yahoo;

reg [3:0] addr_bus;
reg [7:0] data_bus;

initial begin
if(prst)begin
    paddr = 0;
    pwdata = 0;
    pwrite = 0;
    psel = 0;
    //pready = 0;
    //pslverr = 0;
    end
end

always@(posedge pclk) begin
if(penable)begin
    if(pready)begin
        if(pwrite)begin
        paddr <= addr_bus ;
        pwdata <= data_bus;     
        end
        if(pread) begin
        prdata <= yahoo;
        end
    end
end
end

always @(next_state) begin
   state = next_state;
end


always @(posedge pclk) begin
case(state)
S_IDLE:begin
psel = 0;
penable <= 0;
    if (Tr == 1)  begin
        next_state = S_SETUP;
    end
end

S_SETUP:begin
psel = 1;
penable <= 0;
next_state = S_ACCESS;  
end

S_ACCESS:begin
psel = 1;
penable <= 1;
    if (pready == 0)  begin
        next_state = S_ACCESS;  
    end
    if((pready == 1) && (Tr == 1)) begin
        next_state = S_SETUP;
    end     
end
endcase

end
endmodule

///////////////////////////////////////////////////////////////////////////////////

Testbench:

module tb;

reg pclk;
reg prst;
wire [3:0] paddr;
reg [7:0] pwdata;
reg  [7:0] prdata;
reg pwrite;
wire psel;
reg penable;
reg pread;
reg pready;
//reg [2:0] state, next_state;
integer i;
reg [3:0] addr_bus;
reg [7:0] data_bus;
reg [7:0] yahoo;

apb_master dut(pclk,prst,paddr,pwdata,prdata,pwrite,pread,psel,penable,pready);

assign paddr = 0;
initial begin
//TB#1
pclk = 0;
   forever #5 pclk = ~pclk;  //#5 : 5ns
end

initial begin
prst = 1;
#1;
penable = 0;
prdata = 0;
pready = 0;
prst = 0;
#5;
penable <= 1;
wait(pready == 1);
pwrite = 1;
for(i=0;i<10;i=i+1)begin
@(posedge pclk); 
addr_bus = $random;
data_bus = $random; 
end
@(posedge pclk); 
pwrite = 0;
//paddr = 0;
pwdata = 0;
#5;
pread = 1;
pwdata = $random;
#5;
pread = 1;
yahoo = $random;

penable = 0;

end
endmodule

Error: ERROR: [VRFC 10-3236] concurrent assignment to a non-net 'pwdata' is not permitted

Answer 1

等待大神解答