assembly - Can constant non-invariant tsc change frequency across cpu states?

Question

I used to benchmark Linux System Calls with rdtsc to get the counter difference before and after the system call. I interpreted the result as wall clock timer since TSC increments at constant rate and does not stop when entering halt state.

The Invariant TSC concept is described as

The invariant TSC will run at a constant rate in all ACPI P-, C-. and T-states.

Can a constant non-invariant tsc change frequency when changing state from C0 (operating) to C1 (halted)?

My current view is that it cannot change frequency only across Performance(P) states. So applying rdtsc to get wall clock timer for system calls is not reliable when using non-invariant tsc.

I did not find invariant tsc flag in my /proc/cpuinfo, only constant_tsc meaning that it is not necessary invariant.

The source of confusion is the sentence from Intel System Programming manual:

The time stamp counter in newer processors may support an enhancement, referred to as invariant TSC.

So some chips (including mine) have constant, but not invariant tsc.

Answer 1

Starting with Nehalem and Saltwell, all Intel processors support invariant TSC, which means that the TSC is incremented at a constant rate across P-, C-, and T-states (but not necessarily across S-states).

Starting with Pentium 4 Family 0F Model 03, all Intel processors support constant TSC, which means that the TSC is incremented at a constant rate across P- and T-states. The TSC continues to increment in the HLT state (called Auto Halt or C1/Auto Halt). TSC doesn't increment in any other sleep state. This category of processors includes Bonnell.

Older processors don't support constant TSC. The TSC continues to increment in the HLT state, but not in deeper sleep states. On some of these processors, TSC is buggy.

The TSC value may be reinitialized (to some BIOS-dependent value) when waking up from an S-state.

Here is a summary. "Y" means that TSC continues to increment at the same rate across the specified type of states. "N" means that TSC either continues to increment at a different rate or stops incrementing. On a few processors, TSC is incremented in the S3 state and lower (this is called always-on TSC). "N/A" means that TSC is not supported.

                                  |   T   |   P   |C = HLT|C Other|S <= S3|S Other|
---------------------------------------------------
Nehalem+                          |   Y   |   Y   |   Y   |   Y   |   N   |   N   |
Silvermont Merrifield+Moorefield, |   Y   |   Y   |   Y   |   Y   |   Y   |   N   |
Saltwell Penwell+Cloverview
Other Saltwell+                   |   Y   |   Y   |   Y   |   Y   |   N   |   N   |
KNL+                              |   Y   |   Y   |   Y   |   Y   |   N   |   N   |
P4 90nm+                          |   Y   |   Y   |   Y   |   N   |   N   |   N   |
Enhanced Pentium M+               |   Y   |   Y   |   Y   |   N   |   N   |   N   |
Bonnell                           |   Y   |   Y   |   Y   |   N   |   N   |   N   |
Quark X1000                       |   Y   |   N   |   Y   |   N   |   N   |   N   |
KNC                               |   Y   |   N   |   Y   |   N   |   N   |   N   |
P5+                               |   Y   |   N   |   Y   |   N   |   N   |   N   |
Before P5                         |  N/A  |  N/A  |  N/A  |  N/A  |  N/A  |  N/A  |
Other Quark                       |  N/A  |  N/A  |  N/A  |  N/A  |  N/A  |  N/A  |